Integrated circuits (ICs) are known to be used in a wide variety of electronic devices. For example, personal computers, cellular telephones, compact disk players, etc., all include ICs or application specific ICs (ASICs). Also, a disc drive of the type used to interface with a host computer to store and retrieve user data includes ICs that provide a controller for communicating between the host computer and a head-disc assembly of the disc drive.
Complementary Metal Oxide Semiconductor (CMOS) IC devices are prone to “latch-up” due to a parasitic four-layer PNPN path, inherent in most such devices. The parasitic four-layer devices act like a Silicon Control Rectifier (SCR), which once latched cannot be turned off without shutting off the power. Therefore, one technique for recovering from latch-up involves manually turning off or unplugging the power supply to the IC for a short period of time.
A technique for recovering from latch-up without human intervention is described in U.S. Pat. No. 4,761,702 entitled “CMOS LATCH UP RECOVERY CIRCUIT.” Here, an overcurrent shut down circuit is included in a power supply that supplies power to an IC. The overcurrent shut down circuit monitors input current to the IC, and in the event the current exceeds a predetermined threshold level, shuts off the power supply for a predetermined length of time after which the supply is automatically reset.
However, the above technique involves indirectly measuring the input current by sensing current induced in a primary winding of a transformer whose secondary winding is coupled to the IC. This indirect measurement of current introduces inaccuracy in the latch-up detection and recovery process. Further, the power supply is turned back on after the predetermined interval of time even if proper recovery from latch-up has not taken place.
Embodiments of the present invention provide solutions to these and other problems, and offer other advantages over the prior art.